1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory. In particular, it relates to techniques for contacts aligned with a minimum feature size for a processing dimension, such as contacts for data transfer lines of NAND-type electrically erasable programmable read-only memory (EEPROM) or NOR EEPROM, and interconnect layers thereof.
2. Description of the Related Art
FIGS. 1 through 3 show conventional contacts and interconnect layers in, for example, a NAND EEPROM or a nonvolatile semiconductor memory. FIG. 1 shows a aerial pattern view; FIG. 2 shows a schematic cross sectional structure cut along the line I-I in FIG. 1; FIG. 3A shows a schematic cross sectional structure cut along the line II-II in FIG. 1; and FIG. 3B shows a schematic cross sectional structure cut along the line III-III in FIG. 1. In FIG. 1, memory cell transistors are aligned in series along the line I-I between select gate transistors SGS and SGD. Data transfer lines BL are disposed along the line I-I. Word lines WL are disposed in a direction perpendicular to the data transfer lines BL. Circular contacts CSL or elliptic contacts CBL are disposed in a direction perpendicular to the data transfer lines BL. The intervals of the contacts CBL along the line III-III depend on the widths of a device region 148 and a device isolating region 126; and those contacts are aligned at intervals of, for example, 2 F where F denotes a minimum processing dimension. Each of the intervals of those contacts along the line I-I that is perpendicular to the line III-III is longer than each of those along the line III-III, and may be 40 to 100 F, for example.
The contacts CSL and CBL are filled with polycrystalline silicon, which is doped with a high impurity concentration of phosphorus, and the interconnect layer is filled with a metal such as tungsten. The interconnect layer is assumed here to be a data transfer line extension 122, which is longer than 3 F, along the data transfer lines BL. It goes without saying that the interconnect layer can be any kind of long, straight, and fine metallic pattern, and may have a configuration not including via contacts 24 and data transfer line extension 122 but using the data transfer lines BL as interconnects so as to directly form contacts.
In order to provide a lithographic margin, it is preferable that the diameter of each circular contact is greater than F and the width of each interconnect is equal to F (in the case of contacts disposed at intervals of 2 F.) Therefore, on the cross section in the direction perpendicular to the data transfer lines BL (i.e., the cross section cut along the line III-III), the width of each interconnect is shorter than the diameter of each contact.
A method has been disclosed for forming capacitor over bit line (COB) DRAM, which includes the steps of forming drain contact holes for select transistors in a self-aligning manner, depositing a polycide film, and forming drain contacts and bit lines simultaneously through reactive ion etching (RIE) (Japanese Patent Application Laid-open No. Hei 9-3211241).
In addition, a method has been disclosed for a NAND EEPROM, which includes the steps of forming drain contact holes, subjecting a deposited conductive layer to RIE so as to simultaneously form drain contacts and extended electrodes from drain diffusion layers or the like (U.S. Pat. No. 6,310,374).
Furthermore, a method for forming a 1 MOS-1 capacitor DRAM, has been disclosed which includes the steps of covering the top surface of MOS gates with an etching stop layer, forming a planarized insulator film, forming bit line contacts in a self aligning manner, coating with a polycide film and then subjecting the DRAM to RIE so as to simultaneously form bit line contacts and bit lines (U.S. Pat. No. 5,670,404).
Moreover, a configuration of a flash EEPROM, has been disclosed which allows reduction in the minimum interconnect pitch necessary for bit lines by providing a second contact area. The second contact area is a junction between a first conductive layer and a second conductive layer, almost above a charge accumulating electrodes that sandwich a drain region. Bit lines are formed with a shorter width than that of bit line contact areas, and the second contact area is disposed in the expanded space (Japanese Patent Application Laid-open No. Hei 5-198822).
As miniaturization of devices progress, the following problems occur with the conventional technology for forming contacts, as described above, through use of a photolithography processing at only once. When forming contacts through a photolithography processing at only once, circular or elliptical contacts may naturally be formed due to restriction on spatial frequencies of waveforms.
First, as shown in FIG. 4A, there is a problem of bit line contacts CBL, which are disposed along the line III-III, being short-circuited due to deterioration of lithographic margin for the bit line contacts CBL. Circular or elliptical contacts may be easily short-circuited as the distance between adjacent contacts becomes shorter. In addition, when using photolithography and a positive resist, an inter-contact area is partially exposed. As a result, a pattern may be easily lost due to increase in the amount of exposure upon the short inter-contact areas on the cross section along the line III-III.
Alternatively, when reducing the diameter of each contact in order to prevent deterioration in lithographic margin for contacts, it becomes difficult to form contact holes through lithography. In other words, since the exposure intensity for a contact hole pattern is lower than that for a line and space pattern, the exposure sensitivity decreases. As a result, it becomes difficult to form minute contact holes with a sufficient focal depth and an allowable sufficient margin for variation in the amount of exposure. This is apparent from the fact that the spatial frequencies of waveforms having an optical intensity in an arbitrary direction is below the so-called resolution limit, and the minimum line width at the resolution limit cannot be obtained in two directions simultaneously. In short, this problem results from forming circular or elliptical contacts through lithography having two axes with almost the same diameter.
Secondarily, as shown in FIG. 4B, FIG. 1 through FIG. 3A, and FIG. 3B, there is a problem of deterioration in alignment margin. When the intervals between adjacent contacts are short, interconnect layers are easily short-circuited with the adjacent contacts due to misalignment of the interconnect layers with contacts. This problem results from forming interconnect layers and contacts independently through lithography. Referencing FIG. 3B, a region C schematically shows deterioration in the margin for the data transfer line contacts CBL and the interconnects formed of data transfer line extended parts 122. A region A schematically shows that the data transfer line contacts CBL and p-well regions 140 are short-circuited. Referencing FIG. 3A, a region B schematically shows that source line contacts CSL and the p-well regions 140 are short-circuited.
Furthermore, since the contacts are conventionally mask-aligned on a single under-layer, aligning or directly aligning the contacts with gate electrodes, for example, develops indirect alignment of the contacts with device regions that are perpendicular to the gate electrodes. As a result, misalignment of the contacts with the device region increases by the square root of 2 times or more than the amount of misalignment in the case of a direct alignment. Moreover, contacts are formed up to the device isolating region 126 due to misalignment of the device region 148 with a contact region, and a contact material reaches the p-well region 140 under the contact, resulting in deterioration in the withstand voltage between the p-well region 140 and the contacts. Also when the contacts are aligned with the device region 148, the gates and the contacts are indirectly aligned. Therefore, since a sufficient alignment margin must be provided in order to avoid short-circuits between, for example, the data transfer line contacts CBL and the select gate transistor SGD, there is a serious problem that the length of a memory cell array along the data transfer lines BL increases, resulting in an increase in the chip size.